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Aerospace Electronics & Systems Division
CSIR-National Aerospace Laboratories
Bangalore-560017

Lakshmi

Mr.VV.Jagannadham
Senior Scientist

 

 

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About

Mr. V. V. Jagannadham, Senior Scientist at Aerospace Electronics Division. He did his M.Sc. specialization in Electronics from Pt. Ravishankar Shukla University, Raipur and M.Tech specialization in Nanoelectronics from VIT University Vellore.

Awards

NAL foundation day Group award for Excellence in Design, Development and Project execution-2008 "Enhanced v ersion of Floswitch for parallel computing having innovative communication technology Course Offered

 

Email vvjagan@nal.res.in
Telephone (O) +91-80-25086702/6591
Address Aerospace Electronics & Systems Division, National Aerospace Laboratories, HAL Airport Road, Kodihalli, Bengaluru Karnataka - 560 017, INDIA
   
  1. High speed Board Design
  2. Embedded System

Sponsored Projects

In-House Projects Funded by CSIR

Undergraduate Projects

Journal papers

  1. Effect of bipolar pulsed voltage on properties of DLC films deposited by inductively coupled PECVD. VV. Jagannadham, C Anandan, R G. Divya Rao, KS. Rajam, Gargi Raina International Journal of Engineering Research And Applications, ISSN: 2248-9622 Vol. 2, Issue 4, July-august 2012
  2. Power Analysis Of Low Power Virtex 6 FPGA Based Communication FloSwitch Design VV.Jagannadham, Rajalakshmy Sivaramakrishnan International Journal of Engineering Research and Technology, ISSN: 2278-0181, Vol. 2, Issue 11, pp. 233-243
  3. Design of Virtex-7 FPGA based Data Communication Device. Sofia Evelin, V.V Jagannadham, Anandaraj. D and Siddesha.K International Journal of Advance Research in Electronics and Communication Engineering (IJARECE), ISSN: 2278:-909X, Volume 4, Issue 3, March 2015, Page No. 449-452.
  4. Design of Virtex-6 FPGA based Data Concentrator Card. Diganth P, Anandaraj D, Jagannadham V V and Dr. Jayaramaiah G V. International Journal of Advance Research in Electronics and Communication Engineering (IJARECE), ISSN: 2278:-909X, Volume 4, Issue 3, March 2015, Page No. 453-456.
  5. A design of FPGA based intelligent data handling interfacing card. Anandaraj D, Jagannadham V V and Parameshwaran V. International Journal of Engineering Research and Application (IJERA), ISSN: 2248-9622, Vol. 5, Issue 5, May 2015, pp.127-130.

Conference papers

  1. High Speed communication FloSwitch Design Using Virtex-6 FPGA Kamala R MD, Mazharudin, Karthka, Anand, Ashwin MR, Jagannadham V V, Rajshekher JS National Conference on Design Innovations for 3Cs "Compute-Communicate-control ,IETE [The Institute of Electronics and Telecommunication Engineers], MVJ College of Engineering, Bangalore, 5th May 2014, Page no. 38- 41.
  2. Re-Configurable FloSwitch Design Using Multi FPGA Board Mursal Ayub, Jagannadham V V, Rajshekher JS National Conference on Design Innovations for 3Cs "Compute-Communicate-control, IETE [The Institute of Electronics and Telecommunication Engineers], MVJ College of Engineering, Bangalore, 5th May 2014, Page no. 69- 72.

 

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